TDK Lambda | Z+Low Voltage User Manual

9.6.3 Status Byte Register This register summarizes the information from all other status groups as defined in the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation standard. The register can be read either by a serial poll or by *STB?. Both methods return the same data, except for bit 6. Sending *STB? return MSS in bit 6, while polling returns RQS in bit 6. The *CLS command will clear the Status Byte. Bit Signal Meaning 0 BSY Busy bit 1 0 Not used 2 SYS System Error 3 QUES Questionable Status summary bit 4 MAV Message Available summary bit 5 ESB Event Status summary bit 6 Error Information Available This bit is setwhen any error is entered in the SystemError queue. It is readusing the SYSTem:ERRor? Query. Message Available Indicates a message is available in the GPIB output queue. This bit is cleared then the GPIB output buffer is read. Standard Event Status Register This is a summary bit for the ESR. It is set when any of the ESR bits are set, and cleared when the ESR is read. The RQS Bit Whenever the power supply requests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller services the interrupt, RQS is cleared inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed. The MSS Bit This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service Request Enable register. MSS is set whenever the power supply has at least one or more reasons for requesting service. Sending *STB? reads the MSS in bit position 6 of the response. No bits of the Status Byte register are cleared by reading it. 9.6.4 Determining the Cause of a Service Interrupt You can determine the reason for an SRQ by the following actions: Use a serial poll or the *STB? query to determine which summary bits are active. Read the corresponding Event register for each summary bit to determine which events caused the summary bit to be set. When an Event register is read, it is cleared. This also clears the corresponding summary bit. The interrupt will recur until the specific condition that caused the event is removed. If this is not possible, the event may be disabled by programming the corresponding bit of the status group Enable register. A faster way to prevent the interrupt is to disable the service request by programming the appropriate bit of the Service Request Enable register. MSS RQS Master Status summary bit Request Service bit Operation Status summary bit 7 OPER Table 9-4: Status Byte Register

129